Experimental research of a shared memory subsystem with limited queue length for specialized reconfigurable multiprocessor systems

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Alexey I. Martyshkin
Dmitry S. Martens-Atyushev

Abstract

Recently, reconfigurable systems based on field programmable logic devices (FPLDs) have been widely used in high-performance computing. The paper discusses issues related to the experimental research of a shared memory subsystem with a limited queue length of specialized reconfigurable multiprocessor systems using the developed mathematical modelling method. The paper presents the results of the method proposed by the authors for modelling multiprocessor systems based on open queuing networks with limited queue lengths. Based on these conditions, as well as the architectural features of the investigated processor-memory subsystem, expressions are calculated to estimate the exchange time and the resulting delays at each exchange stage. During the research, the main attention was paid to the dependence of the increase in the number of processor nodes in the processor-memory subsystem. As a result, the data obtained showed that the processor growth significantly affects the exchange time, creating a significant load on the common bus, as well as increasing delays at the stages when request transfer operation from the processor to the memory is performed. At the same time, the inadequate behaviour of experimental results and inaccuracy of their values when using the basic modelling method are explicitly tracked, which is reflected in the obtained graphs. Computational experiments were carried out to calculate the probabilistic-temporal characteristics of the "processor-memory" subsystem using the developed mathematical modelling methods. Based on the experimental results, it was determined that the delays occurring in subsystem's nodes and the time of exchange between the processor and memory modules depend on the query parameters and the processor-memory subsystem’s architectural characteristics.

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Contemporary Issues on Management, Engineering and Economics

References

Ali, H., Tariq, U. U., Hardy, J., Zhai, X., Lu, L., Zheng, Y., ... & Antonopoulos, N. (2021). A survey on system level energy optimisation for MPSoCs in IoT and consumer electronics. Computer Science Review, 41, 100416.

Cudennec, L., & Trabelsi, K. (2020, August). Experiments Using a Software-Distributed Shared Memory, MPI and 0MQ over Heterogeneous Computing Resources. In European Conference on Parallel Processing (237-248). Springer, Cham.

Ghose, S., Hsieh, K., Boroumand, A., Ausavarungnirun, R., & Mutlu, O. (2019). The processing-in-memory paradigm: Mechanisms to enable adoption. In Beyond-CMOS Technologies for Next Generation Computer Design (133-194). Springer, Cham.

Lakhani, K. J. (2020). Using GPUDirect RDMA and IPC Shared Memory for Direct DMA in a Client-server (FPGA-GPU) System: One Step Closer to a Fast and Robust DNA Sequencer (Doctoral dissertation, University of California, Davis).

Lant, J., Concatto, C., Attwood, A., Pascual, J. A., Ashworth, M., Navaridas, J., ... & Goodacre, J. (2019). Enabling shared memory communication in networks of MPSoCs. Concurrency and Computation: Practice and Experience, 31(21), e4774.

Lopes, A. S., Brandalero, M., Beck, A. C., & Pereira, M. M. (2019, November). Generating optimized multicore accelerator architectures. In 2019 IX Brazilian Symposium on Computing Systems Engineering (SBESC) (1-8). IEEE.

Martyshkin, A. I. (2021). Pilot Model of the Embedded Reconfigurable Real Time Computing System. International Journal of Engineering Research and Technology, 13(12), 4635-4645.

Martyshkin, A. I., Pashchenko, D. V., Trokoz, D. A., Sinev, M. P., & Svistunov, B. L. (2020). Using queuing theory to describe adaptive mathematical models of computing systems with resource virtualization and its verification using a virtual server with a configuration similar to the configuration of a given model. Bulletin of Electrical Engineering and Informatics, 9(3), 1106-1120.

Martyshkin, A. (2019). Software package for determining characteristics of task managers of reconfigurable computer systems using priority queueing networks. Revista Inclusiones, 463-474.

Nguyen, Q. M., & Sanchez, D. (2021, October). Fifer: Practical Acceleration of Irregular Applications on Reconfigurable Architectures. In MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture (1064-1077).

Reis, J. G., & Fröhlich, A. A. (2020). Towards deterministic FPGA reconfiguration. International Journal of Embedded Systems, 13(2), 236-253.

Sinha, M., Harsha, G. S., Bhattacharyya, P., & Deb, S. (2021). Design space optimization of shared memory architecture in accelerator-rich systems. ACM Transactions on Design Automation of Electronic Systems (TODAES), 26(4), 1-31.